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[
VHDL-FPGA-Verilog
]
usb_jtag-20070128-1751
Description:
网上流传的usb_blaster原理图里的CPLD源码,主要是实现usb时序转换成JATG时序输出！-spreading online usb_blaster tenets of the CPLD Ituri source, usb key is timing converted into JATG sequential output!
Platform:
|
Size:
52224
|
Author:
冯海
|
Hits:
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Search - usb blaster epm7064
Search - usb blaster epm7064